description designed for pulse width modulated (pwm) control of a low voltage dc motor, the A3918 is capable of output currents up to 1.5 a and operating voltages from 2.5 to 9 v. the A3918 has an internal fixed off-time pwm timer that sets a peak current based on the selection of a current sense resistor. an overcurrent output flag is provided that notifies the user when the current in the motor winding reaches the peak current determined by the sense resistor. the fault output does not affect driver operation. the A3918 is provided in a 16-contact, 3 mm 3 mm, 0.75 mm nominal overall height qfn, with exposed pad for enhanced thermal dissipation. it is lead (pb) free, with 100% matte tin leadframe plating. applications include the following: ? digital still cameras (dsc) ? cell phone cameras ? usb powered devices ? battery powered devices features and benefits ? 2.5 to 9 v operation ? internal pwm current control ? synchronous rectification for reduced power dissipation ? peak current output flag ? undervoltage lockout ? low r ds(on) outputs ? small package ? brake mode for dc motor ? sleep function ? crossover-current protection ? thermal shutdown low voltage dc motor driver package: 16-contact qfn (suffix es) functional block diagram A3918 approximate size 3 3 mm 0.75 mm overall height A3918-ds outa outb vbb in1 in2 gnd pad gnd gnd fl vbb 10 f 10 v +5 v vcp cp1 cp2 charge pump r sense sense control logic sense vcp sense regulator 0.1 f 0.1 f cp3 cp4 0.1 f pwm latch and blanking comparator bridge sleep www.datasheet.net/ datasheet pdf - http://www..co.kr/
low voltage dc motor driver A3918 2 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com absolute maximum ratings characteristic symbol notes rating units load supply voltage v bb 9.6 v logic input voltage range v in ?0.3 to 7 v sense voltage v sense continuous 0.5 v pulsed, t w < 1 s1v output current i out may be limited by duty cycle, ambient temperature, and heat sinking. under any set of conditions, do not exceed the specified current rating or a junction temperature of 150c. continuous 1 a peak, dc < 30% 1.5 a operating temperature range t a range s ?20 to 85 c junction temperature t j(max) 150 c storage temperature range t stg ?40 to 150 c selection guide part number packing package A3918sestr-t 1500 pieces per 7-in. reel 16-pin qfn with exposed thermal pad thermal characteristics may require derating at maximum conditions, see application information characteristic symbol test conditions* value units package thermal resistance r ja 4-layer pcb based on jedec standard 42 oc/w *additional thermal information available on the allegro website. terminal list table name number function cp1 15 charge pump capacitor terminal 1 cp2 1 charge pump capacitor terminal 2 cp3 14 charge pump capacitor terminal 3 cp4 16 charge pump capacitor terminal 4 fl 7 current limit flag gnd 2, 6, 8 ground in1 4 control input 1 in2 5 control input 2 outa 12 dmos full-bridge output a outb 10 dmos full-bridge output b pad ? exposed thermal pad sense 11 current sense resistor terminal s l e e p 3 sleep logic input, active low vbb 9 supply voltage vcp 13 reservoir capacitor terminal pin-out diagram pad 12 11 10 9 1 2 3 4 5 6 7 8 16 15 14 13 cp4 cp1 cp3 vcp in2 gnd fl gnd outa sense outb vbb cp2 gnd sleep in1 www.datasheet.net/ datasheet pdf - http://www..co.kr/
low voltage dc motor driver A3918 3 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com electrical characteristics 1,2 valid at t a = 25c and v bb = 2.5 to 9 v, unless otherwise noted characteristics symbol test conditions min. typ. max. units operating voltage range v bb 2.5 ? 9 v vbb supply current i bb i out = 0 ma, pwm = 50 khz, duty cycle = 50% ? 5 ? ma i out = 0 ma, outputs disabled, v bb = 9.6 v ? 3 ? ma sleep mode, v in < 0.4 v ? 150 500 na output resistance r ds(on) source driver, i out = 400 ma , v bb = 3 v, t j = 25c ? 0.52 0.60 source driver, i out = 400 ma , v bb = 3 v, t j = 85c ? 0.78 ? sink driver, i out = 400 ma, v bb = 3 v, t j = 25c ? 0.62 0.74 sink driver, i out = 400 ma, v bb = 3 v, t j = 85c ? 0.93 ? current trip sense voltage v sense fl falling edge 160 200 240 mv clamp diode voltage v f i = 400 ma ? ? 1 v output leakage current i dss outputs, v out = 9 v ?20 ? 20 a control logic logic input voltage v in(1) 2.0 ? 5.5 v v in(0) ? ? 0.8 v logic input current i in(1) v in = 5.5 v ? <100 500 na i in(0) v in = 0.8 v ? low voltage dc motor driver A3918 4 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com i load fl i trip t fl t fl fault asserted fault asserted fault asserted note: timer resets after each reset of the pwm latch. fault timing diagram dc motor operation in1 in2 outa outb function 0 0 off off disabled 1 0 high low forward 0 1 low high reverse 1 1 low low brake control logic www.datasheet.net/ datasheet pdf - http://www..co.kr/
low voltage dc motor driver A3918 5 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com functional description device operation the A3918 is a full-bridge low voltage motor driver capable of operating one high current dc motor. mosfet output stages substantially reduce the voltage drop and the power dissipation of the outputs of the A3918, compared to typical drivers with bipolar transistors. output current can be regulated by pulse width modulating (pwm) the inputs. in addition supporting external pwm of the driver, the A3918 limits the peak current by internally pwming the source driver when the current in the winding exceeds the peak current, which is determined by a sense resistor. a fault output notifies the user that peak current was reached. if internal current limiting is not needed, the sense pin should be shorted to ground. internal circuit protection includes thermal shutdown with hyster- esis, undervoltage lockout, internal clamp diodes, and crossover current protection. the A3918 is designed for portable applications, providing a power-off low current sleep mode and an operating voltage of 2.5 to 9 v. external pwm output current regulation can be achieved by pulse width modulating the inputs. slow decay mode is selected by holding one input high while pwming the other input. hold- ing one input low and pwming the other input results in fast decay. refer to the applications information section for further information. blanking this function blanks the output of the current sense comparator when the outputs are switched. the comparator output is blanked to prevent false overcurrent detections due to reverse recovery currents of the clamp diodes or to switching transients related to the capacitance of the load. the blank time, t blank , is approximately 3 s. sleep mode an active-low control input used to minimize power consumption when the A3918 is not in use. this dis- ables much of the internal circuitry including the output drivers, internal regulator, and charge pump. a logic high allows normal operation. when coming out of sleep mode, wait 1.5 ms before issuing a command, to allow the internal regulator and charge pump to stabilize. enable when all logic inputs are pulled to logic low, the outputs of the bridges are disabled. the charge pump and internal cir- cuitry continue to run when the outputs are disabled. charge pump (cp1, cp2, cp3, and cp4) when supply volt- ages are lower than 3.5 v, the two-stage charge pump triples the input voltage to a maximum of 7 v above the supply. the charge pump is used to create a supply voltage greater than v bb , to drive the source-side dmos gates. for pumping purposes, a 0.1 f ceramic capacitor should be connected between cp1 and cp2, and between cp3 and cp4. a 0.1 uf ceramic capacitor is required between vcp and vbb, to act as a reservoir to operate the high- side dmos devices. thermal shutdown the A3918 will disable the outputs if the junction temperature reaches 165c. when the junction tempera- ture drops 15c, the outputs will be enabled. brake mode when driving dc motors, the A3918 goes into brake mode (turns on both sink drivers) when both of its inputs are high (in1 and in2). there is no protection during braking, so care must be taken to ensure that the peak current during braking does not exceed the absolute maximum current. internal pwm current control the bridge is controlled by a fixed off-time pwm current control circuit that limits the load current to a desired value, i trip . initially, a diagonal pair of source and sink dmos outputs are enabled and current flows through the motor winding and the current sense resistor, r sense . when the voltage across r sense equals the internal reference voltage, the current sense comparator resets the pwm latch, which turns off the source driver. the maximum value of current limiting, i trip (max) , is set by the selection of the sense resistor, r sense , and is approximated by a transconductance function: i trip (max) = 0.2 / r sense . it is critical to ensure the maximum rating on the sense pin (0.5 v) is not exceeded. synchronous rectification when a pwm off-cycle is trig- gered by an internal fixed off-time cycle, load current recirculates in slow decay sr mode. during slow decay, current recirculates through the sink-side fet and the sink-side body diode. the sr feature enables the sink-side fet, effectively shorting out the body diode. the sink driver is not enabled until the source driver is turned off and the crossover delay has expired. this feature helps lower the voltage drop during current recirculation, lower- ing power dissipation in the bridge. overcurrent output flag when the peak current (set by the external resistor) is reached, the fault pin, fl, is pulled low. when a reset of the pwm latch occurs, the fault timer begins. at each pwm latch reset, the timer is reset to zero. after approxi- mately 300 s, if no peak current event was triggered, the timer expires and the fault is released. this ensures that during pwm current limiting, the fault pin remains in a fault state. www.datasheet.net/ datasheet pdf - http://www..co.kr/
low voltage dc motor driver A3918 6 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com applications information reverse/ fast decay reverse/ slow decay forward/ fast decay forward/ slow decay gnd gnd +i reg 0 a -i reg in1 in2 i out(x) v in(1) v in(1) external pwm if external pwm is used, the internal current control can either be disabled by shorting the sense pin to ground, or it can be used to limit the peak current to a value under the stall current to prevent motor heating. external pwm of in1/in2 control is shown in the figure below. pwm current control in fast and slow decay modes www.datasheet.net/ datasheet pdf - http://www..co.kr/
low voltage dc motor driver A3918 7 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com pad A3918 c1 c2 c3 vbb fl gnd vccio in2 in1 outa outb c4 r4 r6 c5 c6 r5 r2 cp4 cp1 cp3 vcp in2 gnd fl gnd outa sense outb cp2 gnd sleep sleep r1 r3 in1 vbb pcb thermal vias trace (2 oz.) signal (1 oz.) ground (1 oz.) thermal (2 oz.) solder A3918 layout the printed circuit board should use a heavy ground- plane. for optimum electrical and thermal performance, the A3918 must be soldered directly onto the board. on the under- side of the A3918 package is an exposed pad, which provides a path for enhanced thermal dissipation. the thermal pad should be soldered directly to an exposed surface on the pcb. thermal vias are used to transfer heat to other layers of the pcb. grounding in order to minimize the effects of ground bounce and offset issues, it is important to have a low impedance single- point ground, known as a star ground , located very close to the device. by making the connection between the exposed thermal pad and the ground plane directly under the A3918, that area becomes an ideal location for a star ground point. a low imped- ance ground will prevent ground bounce during high current operation and ensure that the supply voltage remains stable at the input terminal. the recommended pcb layout shown in the diagram below, illustrates how to create a star ground under the device, to serve both as low impedance ground point and thermal path. the two input capacitors should be placed in parallel, and as close to the device supply pin as possible. the ceramic capaci- tor should be closer to the pin than the bulk capacitor. this is necessary because the ceramic capacitor will be responsible for delivering the high frequency current components. sense pin the sense resistor, r sense , should have a very low impedance path to ground, because it must carry a large current while supporting very accurate voltage measurements by the cur- rent sense comparator. long ground traces will cause additional voltage drops, adversely affecting the ability of the comparator to accurately measure the current in the winding. as shown in the layout below, the sense pin has very short traces to the r sense resistor and very thick, low impedance traces directly to the star ground underneath the device. if possible, there should be no other components on the sense circuit. note: when selecting a value for the sense resistor, be sure not to exceed the maximum voltage on the sense pin of 500 mv. r3 r2 r1 r5 fl in2 vccio in1 c1 c2 c3 u1 gnd vbb outb outa r4 r6 c4 c5 c6 sleep www.datasheet.net/ datasheet pdf - http://www..co.kr/
low voltage dc motor driver A3918 8 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com es package, 16-contact qfn with exposed thermal pad copyright ?2011-2012, allegro microsystems, inc. allegro microsystems, inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to per- mit improvements in the per for mance, reliability, or manufacturability of its products. before placing an order, the user is cautioned to verify that the information being relied upon is current. allegro?s products are not to be used in life support devices or systems, if a failure of an allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. the in for ma tion in clud ed herein is believed to be ac cu rate and reliable. how ev er, allegro microsystems, inc. assumes no re spon si bil i ty for its use; nor for any in fringe ment of patents or other rights of third parties which may result from its use. for the latest version of this document, visit our website: www.allegromicro.com c 0.08 17x a terminal #1 mark area b exposed thermal pad (reference only, terminal #1 identifier appearance at supplier discretion) for reference only, not for tooling use (reference jedec mo-220weed) dimensions in millimeters exact case and lead configuration at supplier discretion within limits shown c reference land pattern layout (reference ipc7351 qfn50p300x300x80-17w4m); all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and pcb layout tolerances; when mounting on a multilayer pcb, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference eia/jedec standard jesd51-5) 16 2 1 a 16 1 2 pcb layout reference view b 1.70 1.70 1.70 1.70 0.30 1 16 0.50 0.90 3.10 3.10 c c seating plane 0.25 +0.05 ?0.07 0.400.10 0.50 0.75 0.05 3.00 0.15 3.00 0.15 d d coplanarity includes exposed thermal pad and terminals www.datasheet.net/ datasheet pdf - http://www..co.kr/
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